XPPU Register Set Overview

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table 16-14:      XPPU Register Summary

Start Address

Register Names

Number of Registers

Description

XPPU Control and Status

0xFF98_0000

CTRL

1

Permission and parity error checking enables.

0xFF98_0004+

ERR_STATUS{1, 2}

2

Poisoned address and Master ID value.

0xFF98_000C

POISON

1

Base address of XPPU sink.

0xFF98_0010+

ISR, IMR, IEN, IDS

4

Interrupt controls: register address decode error, transaction violations, parity errors.

0xFF98_003C

M_MASTER_IDS

1

Number of Master IDs configured.

0xFF98_0040+

M_APERTURE_{32 B, 64 KB, 1 MB, 512 MB}

4

Apertures for IPI, IOP CSRs, Memory, and Quad-SPI.

0xFF98_0050+

BASE_{32 B, 64 KB, 1 MB, 512 MB}

4

Base address for each aperture start address (read-only).

XPPU Aperture Controls

0xFF98_0100+

MASTER_ID{00:19}

20

Master ID profiles.

0xFF98_1000 - 0xFF98_13FF

APERPERM_{000:255}

256

IOP, 64-KB pages.

0xFF98_1400 - 0xFF98_15FF

APERPERM_{256:383}

128

IPI, 32-B pages.

0xFF98_1600 - 0xFF98_163F

APERPERM_{384:399}

16

IOP memory, 64-KB pages.

0xFF98_1640

APERPERM_400

1

Quad-SPI memory, 512 MB.

XPPU Sink Control and Status

0xFF9C_FF00

ERR_STATUS

1

R/W type and Offset address access violations.

0xFF9C_FFEC

ERR_CTRL

1

PSLVERR signaling enable.

0xFF9C_FF10+

ISR, IMR, IER, IDR

4

Interrupt controls: register address decode error.