| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| CTICONTROL | 0x0000000000 | 32 | rwNormal read/write | 0x00000000 | The CTI Control Register enables the CTI. |
| CTIINTACK | 0x0000000010 | 32 | woWrite-only | 0x00000000 | The CTI Interrupt Acknowledge Register is write-only. Any bits written as a 1 cause the ctitrigout output signal to be acknowledged. The acknowledgement is cleared when MAPTRIGOUT is deactivated. This register is used when the ctitrigout is used as a sticky output, that is, no hardware acknowledge is supplied, and a software acknowledge is required. |
| CTIAPPSET | 0x0000000014 | 32 | woWrite-only | 0x00000000 | The CTI Application Trigger Set Register is read/write. A write to this register causes a channel event to be raised, corresponding to the bit written to. |
| CTIAPPCLEAR | 0x0000000018 | 32 | woWrite-only | 0x00000000 | The CTI Interrupt Acknowledge Register is write-only. A write to this register causes a channel event to be cleared, corresponding to the bit written to. |
| CTIAPPPULSE | 0x000000001C | 32 | woWrite-only | 0x00000000 | The CTI Application Pulse Register is write-only. A write to this register causes a channel event pulse, one cticlk period, to be generated, corresponding to the bit written to. The pulse external to the ECT can be extended to multi-cycle by the handshaking interface circuits. This register clears itself immediately, so it can be repeatedly written to without software having to clear it. |
| CTIINEN0 | 0x0000000020 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger 0 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN1 | 0x0000000024 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger 1 to Channel Enable Register enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN2 | 0x0000000028 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN3 | 0x000000002C | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN4 | 0x0000000030 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN5 | 0x0000000034 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN6 | 0x0000000038 | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIINEN7 | 0x000000003C | 32 | rwNormal read/write | 0x00000000 | The CTI Trigger to Channel Enable Register 0 enables the signalling of an event on CTM channels when the core issues a trigger, ctitrigin, to the CTI. Within this register there is one bit for each of the four channels implemented. This register does not affect the application trigger operations. |
| CTIOUTEN0 | 0x00000000A0 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 0 Enable Registers define which channels can generate a ctitrigout[0] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN1 | 0x00000000A4 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 1 Enable Registers define which channels can generate a ctitrigout[1] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN2 | 0x00000000A8 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 2 Enable Registers define which channels can generate a ctitrigout[2] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN3 | 0x00000000AC | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 3 Enable Registers define which channels can generate a ctitrigout[3] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN4 | 0x00000000B0 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 4 Enable Registers define which channels can generate a ctitrigout[4] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN5 | 0x00000000B4 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 5 Enable Registers define which channels can generate a ctitrigout[5] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN6 | 0x00000000B8 | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 6 Enable Registers define which channels can generate a ctitrigout[6] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTIOUTEN7 | 0x00000000BC | 32 | rwNormal read/write | 0x00000000 | The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
| CTITRIGINSTATUS | 0x0000000130 | 32 | roRead-only | 0x00000000 | The CTI Trigger In Status Register provides the status of the ctitrigin inputs. |
| CTITRIGOUTSTATUS | 0x0000000134 | 32 | roRead-only | 0x00000000 | The CTI Trigger Out Status Register provides the status of the ctitrigout outputs. |
| CTICHINSTATUS | 0x0000000138 | 32 | roRead-only | 0x00000000 | The CTI Channel In Status Register provides the status of the ctichin inputs. |
| CTICHOUTSTATUS | 0x000000013C | 32 | roRead-only | 0x00000000 | The CTI Channel Out Status Register provides the status of the CTI ctichout outputs. |
| CTIGATE | 0x0000000140 | 32 | rwNormal read/write | 0x0000000F | The Gate Enable Register prevents the channels from propagating through the CTM to other CTIs. This enables local cross-triggering, for example for causing an interrupt when the ETM trigger occurs. It can be used effectively with CTIAPPSET, CTIAPPCLEAR, and CTIAPPPULSE for asserting trigger outputs by asserting channels, without affecting the rest of the system. On reset, this register is 0xF, and channel propagation is enabled. |
| ASICCTL | 0x0000000144 | 32 | rwNormal read/write | 0x00000000 | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0]. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | CTI Integration mode Control Register |
| CLAIMSET | 0x0000000FA0 | 32 | rwNormal read/write | 0x0000000F | CTI Claim Set |
| CLAIMCLR | 0x0000000FA4 | 32 | rwNormal read/write | 0x00000000 | CTI Claim Clear |
| DEVAFF0 | 0x0000000FA8 | 32 | roRead-only | 0x80000003 | CTI Device Affinity Register 0 |
| DEVAFF1 | 0x0000000FAC | 32 | roRead-only | 0x00000000 | CTI Device Affinity Register 1 |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | CTI Lock Access Register |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | CTI Lock Status Register |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x0000000A | CTI Authentication Status Register |
| DEVARCH | 0x0000000FBC | 32 | roRead-only | 0x47701A14 | CTI Device Architecture Register |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x01040800 | CTI Device ID Register 0 |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000014 | CTI Device Type Register |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000004 | CTI Peripheral Identification Register 4 |
| PIDR5 | 0x0000000FD4 | 32 | roRead-only | 0x00000000 | CTI Peripheral Identification Register 5 |
| PIDR6 | 0x0000000FD8 | 32 | roRead-only | 0x00000000 | CTI Peripheral Identification Register 6 |
| PIDR7 | 0x0000000FDC | 32 | roRead-only | 0x00000000 | CTI Peripheral Identification Register 7 |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x000000A8 | CTI Peripheral Identification Register 0 |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x000000B9 | CTI Peripheral Identification Register 1 |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x0000004B | CTI Peripheral Identification Register 2 |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | CTI Peripheral Identification Register 3 |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x0000000D | CTI Component Identification Register 0 |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000090 | CTI Component Identification Register 1 |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000005 | CTI Component Identification Register 2 |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x000000B1 | CTI Component Identification Register 3 |