AACR (DDR_PHY) Register Description
| Register Name | AACR |
|---|---|
| Offset Address | 0x00000000A0 |
| Absolute Address | 0x00FD0800A0 (DDR_PHY) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x000000FF |
| Description | Anti-Aging Control Register |
AACR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| AAOENC | 31 | rwNormal read/write | 0x0 | Anti-Aging PAD Output Enable Control: Enables if set anti-aging toggling on the pad output enable signal 'ctl_oe_n' going into the DATX8s. This will increase power consumption for the anti-aging feature. |
| AAENC | 30 | rwNormal read/write | 0x0 | Anti-Aging Enable Control: Enables if set the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. |
| AATR | 29:0 | rwNormal read/write | 0xFF | Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. The default value of the AATR corresponds to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. |