ACATRn2 (A53_ETM_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ACATRn2 (A53_ETM_1) Register Description

Register NameACATRn2
Offset Address0x0000000490
Absolute Address 0x00FED40490 (CORESIGHT_A53_ETM_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Comparator Access Type Registers 0-7

ACATRn2 (A53_ETM_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DTBM21rwNormal read/write0x0Controls whether data address comparisons use the data address [63:56] bits
DATARANGE20rwNormal read/write0x0Controls whether a data value comparison uses the single address comparator or the address range comparator:The trace unit ignores this field when DATAMATCH==0b00.Supported only if the corresponding data value comparator is supported, otherwise this bit is RES0.
DATASIZE19:18rwNormal read/write0x0Controls the width of the data value comparison
DATAMATCH17:16rwNormal read/write0x0Controls how the trace unit performs a data value comparison
EXLEVEL_NS15:12rwNormal read/write0x0In Non-secure state, each bit controls whether a comparison can occur for the corresponding exception level:The exception levels are:Bit[12]Exception level 0.Bit[13]Exception level 1.Bit[14]Exception level 2.Bit[15]RAZ/WI. EXLEVEL_NS[3] is never implemented.The content of the field is IMPLEMENTATION DEFINED and is set by the value of IDR3.EXLEVEL_NS. Unimplemented bits are RAZ/WI.
EXLEVEL_S11:8rwNormal read/write0x0In Secure state, each bit controls whether a comparison can occur for the corresponding exception level:The exception levels are:Bit[8]Exception level 0.Bit[9]Exception level 1.Bit[10]RAZ/WI. EXLEVEL_S[2] is never implemented.Bit[11]Exception level 3.The content of the field is IMPLEMENTATION DEFINED and is set by the value of IDR3.EXLEVEL_S. Unimplemented bits are RAZ/WI.
CONTEXT 6:4rwNormal read/write0x0If IDR4.NUMCIDFC > 0 or IDR4.NUMVMIDC > 0, selects a Context ID comparator or VMID comparator:and so on up to 0b111, which indicates comparator 7.The implemented width of this field is determined by the size of whichever of IDR4.NUMVMIDC and IDR4.NUMCIDC is larger. If the largest field is one bit long, then this field implements one bit, bit[4]. If the largest field is four bits long, then this field implements two bits, bits[5:4]. Unimplemented bits within the field are RAZ/WI.If IDR4.NUMCIDFC==0 and IDR4.NUMVMIDC==0, this field is RES0.
CONTEXTTYPE 3:2rwNormal read/write0If IDR4.NUMVMIDC>0 and IDR4.NUMCIDC>0, this field controls whether the trace unit performs a Context ID comparison, a virtual machine identifier (VMID) comparison, or both comparisons:If IDR4.NUMVMIDC==0 and IDR4.NUMCIDC>0, bit [3] is RES0 and bit[2] controls whether the trace unit performs a Context ID comparison, as with cases 0b00 and 0b01 above.If IDR4.NUMVMIDC==0 and IDR4.NUMCIDC==0, both bits are RES0.
TYPE 1:0rwNormal read/write0x0Controls what type of comparison the trace unit performs:If IDR4.SUPPDAC does not indicate that data address comparisons are implemented, then this field is RES0. This means that any comparison performed by this address comparator is an instruction address comparison.