ACBDLR1 (DDR_PHY) Register Description
Register Name | ACBDLR1 |
---|---|
Offset Address | 0x0000000544 |
Absolute Address | 0x00FD080544 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | AC Bit Delay Line Register 1 |
ACBDLR1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:30 | roRead-only | 0x0 | Return zeroes on reads. |
PARBD | 29:24 | rwNormal read/write | 0x0 | Delay select for the BDL on Parity. |
Reserved | 23:22 | roRead-only | 0x0 | Return zeroes on reads. |
A16BD | 21:16 | rwNormal read/write | 0x0 | Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. |
Reserved | 15:14 | roRead-only | 0x0 | Return zeroes on reads. |
A17BD | 13:8 | rwNormal read/write | 0x0 | Delay select for the BDL on Address A[17]. When not in DDR4 mode this pin is connected to CAS. |
Reserved | 7:6 | roRead-only | 0x0 | Return zeroes on reads. |
ACTBD | 5:0 | rwNormal read/write | 0x0 | Delay select for the BDL on ACTN. |