ACBDLR7 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

ACBDLR7 (DDR_PHY) Register Description

Register Name	ACBDLR7
Offset Address	0x000000055C
Absolute Address	0x00FD08055C (DDR_PHY)
Width	32
Type	mixedMixed types. See bit-field details.
Reset Value	0x00000000
Description	AC Bit Delay Line Register 7

ACBDLR7 (DDR_PHY) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
Reserved	31:30	roRead-only	0x0	Reserved. Return zeroes on reads.
A07BD	29:24	rwNormal read/write	0x0	Delay select for the BDL on Address A[7].
Reserved	23:22	roRead-only	0x0	Reserved. Return zeroes on reads.
A06BD	21:16	rwNormal read/write	0x0	Delay select for the BDL on Address A[6].
Reserved	15:14	roRead-only	0x0	Reserved. Return zeroes on reads.
A05BD	13:8	rwNormal read/write	0x0	Delay select for the BDL on Address A[5].
Reserved	7:6	roRead-only	0x0	Reserved. Return zeroes on reads.
A04BD	5:0	rwNormal read/write	0x0	Delay select for the BDL on Address A[4].