ACBDLR8 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ACBDLR8 (DDR_PHY) Register Description

Register NameACBDLR8
Offset Address0x0000000560
Absolute Address 0x00FD080560 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAC Bit Delay Line Register 8

ACBDLR8 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30roRead-only0x0Reserved. Return zeroes on reads.
A11BD29:24rwNormal read/write0x0Delay select for the BDL on Address A[11].
Reserved23:22roRead-only0x0Reserved. Return zeroes on reads.
A10BD21:16rwNormal read/write0x0Delay select for the BDL on Address A[10].
Reserved15:14roRead-only0x0Reserved. Return zeroes on reads.
A09BD13:8rwNormal read/write0x0Delay select for the BDL on Address A[9].
Reserved 7:6roRead-only0x0Reserved. Return zeroes on reads.
A08BD 5:0rwNormal read/write0x0Delay select for the BDL on Address A[8].