ACIOCR2 (DDR_PHY) Register Description
| Register Name | ACIOCR2 |
|---|---|
| Offset Address | 0x0000000508 |
| Absolute Address | 0x00FD080508 (DDR_PHY) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | AC I/O Configuration Register 2 |
ACIOCR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLKGENCLKGATE | 31 | rwNormal read/write | 0x0 | Clock Generator and Control Clock Gate: When set to 1, this signal will gate (stop) the clocks to all registers inside the clock generator block and the Control block. |
| ACOECLKGATE0 | 30 | rwNormal read/write | 0x0 | I/O Output Enable Clock Gate for AC Macro 0: When set to 1, this signal will gate (stop) the clocks to all registers inside the I/O output enable (D) slice. |
| ACPDRCLKGATE0 | 29 | rwNormal read/write | 0x0 | I/O Power-Down Receiver Clock Gate fro AC Macro 0: When set to 1, this signal will gate (stop) the clocks to all registers inside the I/O power down receiver (D) slice. |
| ACTECLKGATE0 | 28 | rwNormal read/write | 0x0 | I/O Terminate Enable Clock Gate for AC Macro 0: When set to 1, this signal will gate (stop) the clocks to all registers inside the I/O termination (D) slice. |
| CKNCLKGATE0 | 27:26 | rwNormal read/write | 0x0 | CK# Clock Gate for AC Macro 0: When set to 1, this signal will gate (stop) the clocks to all registers inside a correspondingly numbered CK# output (D) slice. |
| CKCLKGATE0 | 25:24 | rwNormal read/write | 0x0 | CK Clock Gate for AC Macro 0: When set to 1, this signal will gate (stop) the clocks to all registers inside a correspondingly numbered CK output (D) slice. |
| ACCLKGATE0 | 23:0 | rwNormal read/write | 0x0 | Address/Command Clock Gate for AC Macro 0: When set to 1, this signal will gate (stop) the clock to all registers inside a correspondingly numbered address/command output (D) slice. |