ACLCDLR (DDR_PHY) Register Description
| Register Name | ACLCDLR |
|---|---|
| Offset Address | 0x0000000584 |
| Absolute Address | 0x00FD080584 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | AC Local Calibrated Delay Line Register |
ACLCDLR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| ACD1 | 24:16 | rwNormal read/write | 0x0 | Address/Command Delay for AC Macro 1: Delay select for the address/command (ACD) LCDL. |
| Reserved | 15:9 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| ACD | 8:0 | rwNormal read/write | 0x0 | Address/Command Delay for AC Macro 0: Delay select for the address/command (ACD) LCDL. |