ACMDLR0 (DDR_PHY) Register Description
| Register Name | ACMDLR0 |
|---|---|
| Offset Address | 0x00000005A0 |
| Absolute Address | 0x00FD0805A0 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | AC Master Delay Line Register 0 |
ACMDLR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| TPRD | 24:16 | rwNormal read/write | 0x0 | Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. |
| Reserved | 15:9 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| IPRD | 8:0 | rwNormal read/write | 0x0 | Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. |