ACMDLR1 (DDR_PHY) Register Description
Register Name | ACMDLR1 |
---|---|
Offset Address | 0x00000005A4 |
Absolute Address | 0x00FD0805A4 (DDR_PHY) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | AC Master Delay Line Register 1 |
ACMDLR1 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:25 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
MDLD1 | 24:16 | rwNormal read/write | 0x0 | MDL Delay for AC Macro 1: Delay select for the LCDL for the Master Delay Line. |
Reserved | 15:9 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
MDLD | 8:0 | rwNormal read/write | 0x0 | MDL Delay for AC Macro 0: Delay select for the LCDL for the Master Delay Line. |