ACPU_CTRL (CRF_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ACPU_CTRL (CRF_APB) Register Description

Register NameACPU_CTRL
Offset Address0x0000000060
Absolute Address 0x00FD1A0060 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x03000400
DescriptionAPU MPCore Clock Generator Control.

Register is write protected by crf_apb.crf_wprot [active].

ACPU_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CLKACT_HALF25rwNormal read/write0x1Clock active control for half-speed APU Clock.
0: disable. Clock stop.
1: enable.
CLKACT_FULL24rwNormal read/write0x1Clock active control for full-speed APU Clock.
0: disable. Clock stop.
1: enable.
DIVISOR013:8rwNormal read/write0x46-bit divider.
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: APLL
010: DPLL
011: VPLL