APLL_CTRL (CRF_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

APLL_CTRL (CRF_APB) Register Description

Register NameAPLL_CTRL
Offset Address0x0000000020
Absolute Address 0x00FD1A0020 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00012C09
DescriptionAPLL Clock Unit Control

APLL_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
POST_SRC26:24rwNormal read/write0x0Select the pass-thru clock source for PLL Bypass mode.
0xx: PS_REF_CLK
100: VIDEO_REF_CLK
101: ALT_REF_CLK
110: AUX_REF_CLK
111: GT_REF_CLK
PRE_SRC22:20rwNormal read/write0x0Select the clock source for PLL input.
0xx: PS_REF_CLK
100: VIDEO_REF_CLK
101: ALT_REF_CLK
110: AUX_REF_CLK
111: GT_REF_CLK
DIV216rwNormal read/write0x1Enable the divide by 2 function inside of the PLL.
0: no effect.
1: divide clock by 2.
Note: this does not change the VCO frequency, just the output frequency.
FBDIV14:8rwNormal read/write0x2CFeedback divisor integer portion for the PLL.
BYPASS 3rwNormal read/write0x1PLL Clock Bypass Mode.
0: normal PLL mode; the source clock is selected using [PRE_SRC].
1: bypass the PLL; the source clock is selected using [POST_SRC].
RESET 0rwNormal read/write0x1PLL reset.
0: active.
1: reset.
Note: Program the PLL into bypass mode before resetting the PLL.