APLL_FRAC_CFG (CRF_APB) Register Description
Register Name | APLL_FRAC_CFG |
---|---|
Offset Address | 0x0000000028 |
Absolute Address | 0x00FD1A0028 (CRF_APB) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Fractional control for the PLL |
APLL_FRAC_CFG (CRF_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ENABLED | 31 | rwNormal read/write | 0x0 | Fractional SDM bypass control. 0: PLL is in integer mode and it ignores all fractional data. 1: PLL is in fractional mode and uses [DATA] bitfield for the fractional portion of the feedback divider. |
DATA | 15:0 | rwNormal read/write | 0x0 | Fractional value for the Feedback value. |