ASICCTL (CTI) Register Description
| Register Name | ASICCTL |
|---|---|
| Offset Address | 0x0000000144 |
| Absolute Address |
0x00FEBF8144 (CORESIGHT_R5_CTI_0) 0x00FEBF9144 (CORESIGHT_R5_CTI_1) 0x00FE990144 (CORESIGHT_SOC_CTI_0) 0x00FE9A0144 (CORESIGHT_SOC_CTI_1) 0x00FE9B0144 (CORESIGHT_SOC_CTI_2) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0]. |
ASICCTL (CTI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ASICCTL | 7:0 | rwNormal read/write | 0x0 | Implementation-defined ASIC control, value written to the register is output on asicctl[7:0].If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the Device ID Register. This is done within a Verilog define EXTMUXNUM. |