AUDIO_SOFT_RESET (DISPLAY_PORT) Register Description
| Register Name | AUDIO_SOFT_RESET |
|---|---|
| Offset Address | 0x000000CC00 |
| Absolute Address | 0x00FD4ACC00 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Audio Soft reset reigster. |
AUDIO_SOFT_RESET (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0 | |
| EXTRA_BS_CONTROL | 2 | rwNormal read/write | 0 | Setting this bit to 1 will bypass the extra BS on link. This is a non-reset flop. SW has to set this bit to 0 after power on |
| LINE_RESET_DISABLE | 1 | rwNormal read/write | 0 | Set the bit to 1 to disable the end of line reset for reduced blanking resolutions. As per CVT standard, the reduced blanking resolutions blanking period is less than 20% of HTOTAL and it has either blanking period as 80/160 and hres%8 = 0 Reduced blanking version 1 (RB) resolutions have HBLANK as 160 Reduced blanking version 2 (RB 2) resolutions have H BLANK as 80 This is a non-reset flop. SW has to set this bit to 0 after power on |
| AUDIO_SRST | 0 | rwNormal read/write | 0 | Set this bit to 1 to reset audio pipe. Required whenever audio from DPDMA is disabled. Clear this bit to deassert reset. Note that when ever audio soft reset is used, after deassertion of Audio soft reset, all the registers related to Audio programming need to be cleared to 0 and rewritten with correct values. This is a non-reset flop. SW has to set this bit to 0 after power on |