AUD_PATTERN_SELECT1 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AUD_PATTERN_SELECT1 (DISPLAY_PORT) Register Description

Register NameAUD_PATTERN_SELECT1
Offset Address0x000000B104
Absolute Address 0x00FD4AB104 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAUD_CH1_PAT_SELECT

AUD_PATTERN_SELECT1 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0Reserved
PATTERN 1:0rwNormal read/write0x0Audio pattern generated on ch1. This bit is valid only when 0xB070 is selected for internal pattern generator (Bits 5:4 =2].
00b: Ping pattern. Alternate silence and sine for 250ms
01b: Sine pattern (2kHz when audio frequency = 48kHz. For 44.1kHz, frequency is almost = 2kHz)
10b: Silence