AUXCR (STM) Register Description
| Register Name | AUXCR |
|---|---|
| Offset Address | 0x0000000E94 |
| Absolute Address | 0x00FE9C0E94 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Implementation Defined STM controls. |
AUXCR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| QHWEVOVERRIDE | 7 | rwNormal read/write | 0x0 | Provides override control for the Q-Channels: 0: no override. 1: override. |
| PRIORINVDIS | 2 | rwNormal read/write | 0x0 | Controls arbitration between AXI and HW during flush: 0: inversion enabled. 1: inversion disabled. |
| ASYNCPE | 1 | rwNormal read/write | 0x0 | ASYNC priority: 0: disable. 1: enable. |
| FIFOAF | 0 | rwNormal read/write | 0x0 | Auto-flush: 0: disable. 1: enable. |