AUXCTLR (A53_ETM_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AUXCTLR (A53_ETM_3) Register Description

Register NameAUXCTLR
Offset Address0x0000000018
Absolute Address 0x00FEF40018 (CORESIGHT_A53_ETM_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAuxiliary Control Register

AUXCTLR (A53_ETM_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
COREIFEN 7rwNormal read/write0x0Keep core interface enabled regardless of trace enable register state
AUTHNOFLUSH 5rwNormal read/write0x0Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior.
TSNODELAY 4rwNormal read/write0x0Do not delay timestamp insertion based on FIFO depth.
SYNCDELAY 3rwNormal read/write0x0Delay periodic synchronization if FIFO is more than half-full.
OVFLW 2rwNormal read/write0x0Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior.
IDLEACK 1rwNormal read/write0x0Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior.
AFREADY 0rwNormal read/write0x0Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state.