Field Name | Bits | Type | Reset Value | Description |
COREIFEN | 7 | rwNormal read/write | 0x0 | Keep core interface enabled regardless of trace enable register state |
AUTHNOFLUSH | 5 | rwNormal read/write | 0x0 | Do not flush trace on de-assertion of authentication inputs. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior. |
TSNODELAY | 4 | rwNormal read/write | 0x0 | Do not delay timestamp insertion based on FIFO depth. |
SYNCDELAY | 3 | rwNormal read/write | 0x0 | Delay periodic synchronization if FIFO is more than half-full. |
OVFLW | 2 | rwNormal read/write | 0x0 | Force an overflow if synchronization is not completed when second synchronization becomes due. When this bit is set to 1 the trace unit behavior deviates from architecturally-specified behavior. |
IDLEACK | 1 | rwNormal read/write | 0x0 | Force idle-drain acknowledge high CPU does not wait for trace to drain before entering WFX state. When this bit is set to 1 trace unit behavior deviates from architecturally-specified behavior. |
AFREADY | 0 | rwNormal read/write | 0x0 | Always respond to AFREADY immediately. Does not have any interaction with FIFO draining even in WFI state. |