AV_BUF_AUD_VID_CLK_SOURCE (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AV_BUF_AUD_VID_CLK_SOURCE (DISPLAY_PORT) Register Description

Register NameAV_BUF_AUD_VID_CLK_SOURCE
Offset Address0x000000B120
Absolute Address 0x00FD4AB120 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAV_BUF_AUD_VID_CLK_SOURCE: When live video from PL is absent, then the internal clock shall be video pipeline clock. If the live video is present, then clock from PL shall be the video pipe line clock. Similarly for the audio we can select from either PS or PL clock

AV_BUF_AUD_VID_CLK_SOURCE (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:3razRead as zero0x0
VID_TIMING_SRC 2rwNormal read/write0x0Bits[2] -
- 0: Timing from PL (Default)
- 1: Internal Timing
Typical use case is, when Video from memory is blended and output to PL
AUD_CLK_SRC 1rwNormal read/write0x0Bits[1] -
- 0: clock from PL (Default)
- 1: Clock from PS
VID_CLK_SRC 0rwNormal read/write0x0Bits[0] -
- 0: clock from PL (Default) dp_live_video_in_clk
- 1: Clock from PS(dp_vtc_pixel_clk_in)