AV_BUF_AUD_VID_CLK_SOURCE (DISPLAY_PORT) Register Description
Register Name | AV_BUF_AUD_VID_CLK_SOURCE |
---|---|
Offset Address | 0x000000B120 |
Absolute Address | 0x00FD4AB120 (DISPLAY_PORT) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | AV_BUF_AUD_VID_CLK_SOURCE: When live video from PL is absent, then the internal clock shall be video pipeline clock. If the live video is present, then clock from PL shall be the video pipe line clock. Similarly for the audio we can select from either PS or PL clock |
AV_BUF_AUD_VID_CLK_SOURCE (DISPLAY_PORT) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:3 | razRead as zero | 0x0 | |
VID_TIMING_SRC | 2 | rwNormal read/write | 0x0 | Bits[2] - - 0: Timing from PL (Default) - 1: Internal Timing Typical use case is, when Video from memory is blended and output to PL |
AUD_CLK_SRC | 1 | rwNormal read/write | 0x0 | Bits[1] - - 0: clock from PL (Default) - 1: Clock from PS |
VID_CLK_SRC | 0 | rwNormal read/write | 0x0 | Bits[0] - - 0: clock from PL (Default) dp_live_video_in_clk - 1: Clock from PS(dp_vtc_pixel_clk_in) |