AV_BUF_LIVE_GFX_CONFIG (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AV_BUF_LIVE_GFX_CONFIG (DISPLAY_PORT) Register Description

Register NameAV_BUF_LIVE_GFX_CONFIG
Offset Address0x000000B234
Absolute Address 0x00FD4AB234 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionProgrammable option to configure Cb or Cr first, when YUV422 mode is enabled

AV_BUF_LIVE_GFX_CONFIG (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9razRead as zero0x0
CB_FIRST 8rwNormal read/write0x0: when bit 0 =1, on live graphics, Cb is received first. When bit 0 = Cr is sent first.
Reserved 7:6razRead as zero0x0
FORMAT 5:4rwNormal read/write0x0Bits [5:4] -
00: RGB
01: YUV 444
10: YUV422
11: Y Only
Reserved 3razRead as zero0x0
BPC 2:0rwNormal read/write0x0Bits[2:0]-
000: BPC = 6
001: BPC = 8
010: BPC = 10
011: BPC = 12