AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (DISPLAY_PORT) Register Description

Register NameAV_BUF_STC_VIDEO_VSYNC_TS_REG0
Offset Address0x000000B03C
Absolute Address 0x00FD4AB03C (DISPLAY_PORT)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAV_BUF_STC_VIDEO_VSYNC_TS_REG0: STC TS with VSYNC event

AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VSYNC_TS031:0roRead-only0x0Bits [31:0] of VSYNC TS register