AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (DISPLAY_PORT) Register Description

Register NameAV_BUF_STC_VIDEO_VSYNC_TS_REG1
Offset Address0x000000B040
Absolute Address 0x00FD4AB040 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAV_BUF_STC_VIDEO_VSYNC_TS_REG1: STC TS with VSYNC event

AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10razRead as zero0x0
VSYNC_TS1 9:0roRead-only0x0Bits [9:0] of TS register.
-
=Bits [41:32] of VSYNC TS register