AV_CHBUF0 (DISPLAY_PORT) Register Description
| Register Name | AV_CHBUF0 |
|---|---|
| Offset Address | 0x000000B010 |
| Absolute Address | 0x00FD4AB010 (DISPLAY_PORT) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | AV_CHBUF0: Channel Enable, flush and Burst length to be programmed based on video formats. Each channel can be programmed with independent BL Channel 0: must be always enabled for any video mode. Channel 1 and 2: should be enabled for planar modes. Channel 3: for graphics. Channel 4 and 5: for audio modes |
AV_CHBUF0 (DISPLAY_PORT) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:7 | razRead as zero | 0x0 | |
| BURST_LEN | 6:2 | rwNormal read/write | 0x0 | Burst length: Allowed values are 0,1,3,7,15. (correspond to 1,2,4,8,16) |
| FLUSH | 1 | rwNormal read/write | 0x0 | Flush |
| EN | 0 | rwNormal read/write | 0x0 | Enable |