| Field Name | Bits | Type | Reset Value | Description |
|---|
| WrBurstLen | 11:8 | rwNormal read/write | 0x0 | This field indicates the maximum number of data transfers that can occur within each burst initiated by the TMC on the AXI interface. The Write burst initiated on the AXI can be of lesser length that the programmed value in the case when the formatter has stopped due to a stop condition having occurred. Programming this field to a burst length value greater than the write buffer depth will result in a burst length that is equal to the write buffer depth.The burst length programmed must be compatible with the trace buffer size and the AXI data width such that the total number of bytes of data transferred in a burst is not greater than the trace buffer size or, if Scatter_Gather mode is enabled, is not greater than 4K bytes. Programming an incompatible burst length will result in Unpredictable behavior. It is recommended that this value be set to no more than one half the write buffer depth. Also, it is recommended that this value be set to enable an AXI burst of atleast one frame of trace data. 0x0 - 1 data transfer per burst. 0x1 - Maximum of 2 data transfers per burst..0xF - Maximum of 16 data transfers per burst.Default - 0x0. |
| ScatterGatherMode | 7 | rwNormal read/write | 0x0 | This bit indicates whether trace memory is accessed as a single buffer in system memory or as a linked-list based scatter-gather memory. This is ignored when the TMC is in Disabled state (TraceCaptEn=0 and TMCReady=1). |
| CacheCtrlBit3 | 5 | rwNormal read/write | 0x0 | This bit controls the value driven on the ARCACHEM[3]/AWCACHEM[3] signal on the AXI interface when performing AXI transfers. If CacheCtrlBit1 is 0, then this bit must also be 0 to comply with AXI protocol. Setting this bit to 1 when the CacheCtrlBit1 is 0 will result in Unpredictable behavior. |
| CacheCtrlBit2 | 4 | rwNormal read/write | 0x0 | This bit controls the value driven on the ARCACHEM[2]/AWCACHEM[2] signal on the AXI interface when performing AXI transfers. If CacheCtrlBit1 is 0, then this bit must also be 0 to comply with AXI protocol. Setting this bit to 1 when the CacheCtrlBit1 is 0 will result in Unpredictable behavior. |
| CacheCtrlBit1 | 3 | rwNormal read/write | 0x0 | This bit controls the value driven on the ARCACHEM[1]/AWCACHEM[1] signal on the AXI interface when performing AXI transfers. |
| CacheCtrlBit0 | 2 | rwNormal read/write | 0x0 | This bit controls the value driven on the ARCACHEM[0]/AWCACHEM[0] signal on the AXI interface when performing AXI transfers. |
| ProtCtrlBit1 | 1 | rwNormal read/write | 0x0 | This bit controls the value driven on ARPROTM[1]/AWPROTM[1] on the AXI interface when performing AXI transfers. |
| ProtCtrlBit0 | 0 | rwNormal read/write | 0x0 | This bit controls the value driven on ARPROTM[0]/AWPROTM[0] on the AXI interface when performing AXI transfers. |