AXIPCIE_DMA Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

AXIPCIE_DMA Module Description

Module Name	AXIPCIE_DMA Module
Modules of this Type	AXIPCIE_DMA0, AXIPCIE_DMA1, AXIPCIE_DMA2, AXIPCIE_DMA3
Base Addresses	0x00FD0F0000 (AXIPCIE_DMA0) 0x00FD0F0080 (AXIPCIE_DMA1) 0x00FD0F0100 (AXIPCIE_DMA2) 0x00FD0F0180 (AXIPCIE_DMA3)
Description	AXI PCIe Bridge - DMA Channel

AXIPCIE_DMA Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
DMA_CHANNEL_SRC_Q_PTR_LO	0x0000000000	32	rwNormal read/write	0x00000000	Queue Base Address Low
DMA_CHANNEL_SRC_Q_PTR_HI	0x0000000004	32	rwNormal read/write	0x00000000	Queue Base Address High
DMA_CHANNEL_SRC_Q_SIZE	0x0000000008	32	rwNormal read/write	0x00000000	Queue Size
DMA_CHANNEL_SRC_Q_LIMIT	0x000000000C	32	rwNormal read/write	0x00000000	Queue Limit Pointer
DMA_CHANNEL_DST_Q_PTR_LO	0x0000000010	32	rwNormal read/write	0x00000000	Queue Base Address Low
DMA_CHANNEL_DST_Q_PTR_HI	0x0000000014	32	rwNormal read/write	0x00000000	Queue Base Address High
DMA_CHANNEL_DST_Q_SIZE	0x0000000018	32	rwNormal read/write	0x00000000	Queue Size
DMA_CHANNEL_DST_Q_LIMIT	0x000000001C	32	rwNormal read/write	0x00000000	Queue Limit Pointer
DMA_CHANNEL_STAS_Q_PTR_LO	0x0000000020	32	rwNormal read/write	0x00000000	Queue Base Address Low
DMA_CHANNEL_STAS_Q_PTR_HI	0x0000000024	32	rwNormal read/write	0x00000000	Queue Base Address High
DMA_CHANNEL_STAS_Q_SIZE	0x0000000028	32	rwNormal read/write	0x00000000	Queue Size
DMA_CHANNEL_STAS_Q_LIMIT	0x000000002C	32	rwNormal read/write	0x00000000	Queue Limit Pointer
DMA_CHANNEL_STAD_Q_PTR_LO	0x0000000030	32	rwNormal read/write	0x00000000	Queue Base Address Low
DMA_CHANNEL_STAD_Q_PTR_HI	0x0000000034	32	rwNormal read/write	0x00000000	Queue Base Address High
DMA_CHANNEL_STAD_Q_SIZE	0x0000000038	32	rwNormal read/write	0x00000000	Queue Size
DMA_CHANNEL_STAD_Q_LIMIT	0x000000003C	32	rwNormal read/write	0x00000000	Queue Limit Pointer
DMA_CHANNEL_SRC_Q_NEXT	0x0000000040	32	rwNormal read/write	0x00000000	Queue Next Pointer
DMA_CHANNEL_DST_Q_NEXT	0x0000000044	32	rwNormal read/write	0x00000000	Queue Next Pointer
DMA_CHANNEL_STAS_Q_NEXT	0x0000000048	32	rwNormal read/write	0x00000000	Queue Next Pointer
DMA_CHANNEL_STAD_Q_NEXT	0x000000004C	32	rwNormal read/write	0x00000000	Write only to initialize DMA Channel
DMA_CHANNEL_SCRATCH0	0x0000000050	32	rwNormal read/write	0x00000000	Scratchpad Register
DMA_CHANNEL_SCRATCH1	0x0000000054	32	rwNormal read/write	0x00000000	Scratchpad Register
DMA_CHANNEL_SCRATCH2	0x0000000058	32	rwNormal read/write	0x00000000	Scratchpad Register
DMA_CHANNEL_SCRATCH3	0x000000005C	32	rwNormal read/write	0x00000000	Scratchpad Register
DMA_CHANNEL_PCIE_INTERRUPT_CONTROL	0x0000000060	32	mixedMixed types. See bit-field details.	0x00000000	PCI Express Interrupt Control
DMA_CHANNEL_PCIE_INTERRUPT_STATUS	0x0000000064	32	mixedMixed types. See bit-field details.	0x00000000	PCIe Interrupt Status
DMA_CHANNEL_AXI_INTERRUPT_CONTROL	0x0000000068	32	mixedMixed types. See bit-field details.	0x00000000	PCI Express Interrupt Control
DMA_CHANNEL_AXI_INTERRUPT_STATUS	0x000000006C	32	mixedMixed types. See bit-field details.	0x00000000	AXI Interrupt Status
DMA_CHANNEL_PCIE_INTERRUPT_ASSERT	0x0000000070	32	mixedMixed types. See bit-field details.	0x00000000	PCIe Interrupt Assertion.
DMA_CHANNEL_AXI_INTERRUPT_ASSERT	0x0000000074	32	mixedMixed types. See bit-field details.	0x00000000	AXI Interrupt Assertion.
DMA_CHANNEL_DMA_CONTROL	0x0000000078	32	mixedMixed types. See bit-field details.	0x00000000	DMA Channel Control
DMA_CHANNEL_DMA_STATUS	0x000000007C	32	roRead-only	0x00008000	DMA Channel Status