AXIPCIE_EGRESS Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AXIPCIE_EGRESS Module Description

Module NameAXIPCIE_EGRESS Module
Modules of this TypeAXIPCIE_EGRESS0, AXIPCIE_EGRESS1, AXIPCIE_EGRESS2, AXIPCIE_EGRESS3, AXIPCIE_EGRESS4, AXIPCIE_EGRESS5, AXIPCIE_EGRESS6, AXIPCIE_EGRESS7
Base Addresses 0x00FD0E0C00 (AXIPCIE_EGRESS0)
0x00FD0E0C20 (AXIPCIE_EGRESS1)
0x00FD0E0C40 (AXIPCIE_EGRESS2)
0x00FD0E0C60 (AXIPCIE_EGRESS3)
0x00FD0E0C80 (AXIPCIE_EGRESS4)
0x00FD0E0CA0 (AXIPCIE_EGRESS5)
0x00FD0E0CC0 (AXIPCIE_EGRESS6)
0x00FD0E0CE0 (AXIPCIE_EGRESS7)
DescriptionPCIe Bridge - Egress Addr Translation

AXIPCIE_EGRESS Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
TRAN_EGRESS_CAPABILITIES0x000000000032roRead-only0x1F0C0001Egress AXI Translation - Capabilities
TRAN_EGRESS_STATUS0x000000000432roRead-only0x00000000Egress AXI Translation - Status
TRAN_EGRESS_CONTROL0x000000000832mixedMixed types. See bit-field details.0x00000000Egress AXI Translation - Control
TRAN_EGRESS_SRC_BASE_LO0x000000001032mixedMixed types. See bit-field details.0x00000000Egress AXI Translation - Source Address Low
TRAN_EGRESS_SRC_BASE_HI0x000000001432rwNormal read/write0x00000000Egress AXI Translation - Source Address High
TRAN_EGRESS_DST_BASE_LO0x000000001832mixedMixed types. See bit-field details.0x00000000Egress AXI Translation - Destination Address Low
TRAN_EGRESS_DST_BASE_HI0x000000001C32rwNormal read/write0x00000000Egress AXI Translation - Destination Address High