AXIPCIE_INGRESS Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AXIPCIE_INGRESS Module Description

Module NameAXIPCIE_INGRESS Module
Modules of this TypeAXIPCIE_INGRESS0, AXIPCIE_INGRESS1, AXIPCIE_INGRESS2, AXIPCIE_INGRESS3, AXIPCIE_INGRESS4, AXIPCIE_INGRESS5, AXIPCIE_INGRESS6, AXIPCIE_INGRESS7
Base Addresses 0x00FD0E0800 (AXIPCIE_INGRESS0)
0x00FD0E0820 (AXIPCIE_INGRESS1)
0x00FD0E0840 (AXIPCIE_INGRESS2)
0x00FD0E0860 (AXIPCIE_INGRESS3)
0x00FD0E0880 (AXIPCIE_INGRESS4)
0x00FD0E08A0 (AXIPCIE_INGRESS5)
0x00FD0E08C0 (AXIPCIE_INGRESS6)
0x00FD0E08E0 (AXIPCIE_INGRESS7)
DescriptionPCIe Bridge - Ingress Addr Translation

AXIPCIE_INGRESS Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
TRAN_INGRESS_CAPABILITIES0x000000000032roRead-only0x1F0C0001Ingress AXI Translation - Capabilities
TRAN_INGRESS_STATUS0x000000000432roRead-only0x00000000Ingress AXI Translation - Status
TRAN_INGRESS_CONTROL0x000000000832mixedMixed types. See bit-field details.0x00000000Ingress AXI Translation - Control
TRAN_INGRESS_SRC_BASE_LO0x000000001032mixedMixed types. See bit-field details.0x00000000Ingress AXI Translation - Source Address Low
TRAN_INGRESS_SRC_BASE_HI0x000000001432rwNormal read/write0x00000000Ingress AXI Translation - Source Address High
TRAN_INGRESS_DST_BASE_LO0x000000001832mixedMixed types. See bit-field details.0x00000000Ingress AXI Translation - Destination Address Low
TRAN_INGRESS_DST_BASE_HI0x000000001C32rwNormal read/write0x00000000Ingress AXI Translation - Destination Address High