BANK3_CTRL2 (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BANK3_CTRL2 (CRL_APB) Register Description

Register NameBANK3_CTRL2
Offset Address0x0000000278
Absolute Address 0x00FF5E0278 (CRL_APB)
Width10
TyperwNormal read/write
Reset Value0x000003FF
DescriptionSchmitt/CMOS input select for DIO bank 3

Schmitt/CMOS input select: 0: normal CMOS 1: Schmitt trigger input Note: Each bit applies to a single I/O pin.

BANK3_CTRL2 (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
schmitt_cmos_n 9:0rwNormal read/write0x3FFBit[9]: TCK
Bit[8]: TDI
Bit[7]: TMS
Bit[6]: TDO
Bit[5]: SRST
Bit[4]: PROG
Bit[3]: INIT
Bit[2]: DONE
Bit[1]: ERROR_OUT
Bit[0]: ERROR_STS