BCR5 (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BCR5 (R5_DBG_0) Register Description

Register NameBCR5
Offset Address0x0000000154
Absolute Address 0x00FEBF0154 (CORESIGHT_R5_DBG_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBreakpoint Control Register 5

BCR5 (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Breakpoint_address_mask28:24rwNormal read/write0This field sets a breakpoint on a range of addresses by masking lower order address bits out of the breakpoint comparison.
b00000 = no mask
b00001 = Reserved
b00010 = Reserved
b00011 = 0x00000007 mask for instruction address
b00100 = 0x0000000F mask for instruction address
b00101 = 0x0000001F mask for instruction address
..
b11111 = 0x7FFFFFFF mask for instruction address.
If BCR[28:24] is not set to b00000, thenBCR[8:5] must be set to b1111. Otherwise the behavior is Unpredictable. In addition, if BCR[28:24] is not set to b00000, then the corresponding BVR bits that are not being included in the comparison Should Be Zero.
Otherwise the behavior is Unpredictable. Ifthis BRP is programmed for context ID comparison, this field must be set to b00000.Otherwise the behavior is Unpredictable. There is no encoding for a full 32-bit mask but the same effect of a break anywherebreakpoint can be achieved by setting BCR[22] to 1 and BCR[8:5] to b0000.
M22:20rwNormal read/write0Meaning of BVR:
b000 = instruction address match
b001 = linked instruction address match
b010 = unlinked context ID
b011 = linked context ID
b100 = instruction address mismatch
b101 = linked instruction address mismatch
b11x = reserved.
Linked_BRP_number19:16rwNormal read/write0The binary number encoded here indicates another BRPto link this one with.
Note
. if a BRP is linked with itself,it is Unpredictable whether a breakpoint debug event is generated
. if this BRP is linked to another BRP that is not configured for linked context ID matching, it is
Unpredictable whether a breakpoint debug event is generated.
Byte_address_select 8:5rwNormal read/write0For breakpoints programmed to match an instruction address, the debugger must write a word-aligned address to the BVR. You can then use this field toprogram the breakpoint soit hits only if certain byte addresses are accessed.
If the BRP is programmed for instruction address match:
b0000 = the breakpoint never hits
bxxx1 = the breakpoint hits if the byte at address (BVR & 0xFFFFFFFC) +0 is accessed
bxx1x = the breakpoint hits if the byte at address (BVR & 0xFFFFFFFC) +1 is accessed
bx1xx = the breakpoint hits if the byte at address (BVR & 0xFFFFFFFC) +2 is accessed
b1xxx = the breakpoint hits if the byte at address (BVR & 0xFFFFFFFC) +3 is accessed
b1111 = the breakpoint hits if any of the four bytes starting at address (BVR & 0xFFFFFFFC) +0 is accessed.
If the BRP is programmed for instruction address mismatch, the breakpoint hits where the corresponding instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint.
If the BRP is programmed for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected.
Writing a value to BCR[8:5] so that BCR[8] is not equal to BCR[7] or BCR[6] isnot equal to BCR[5] has Unpredictable results.
S 2:1rwNormal read/write0Supervisor access control. The breakpoint can be conditioned on the mode of the processor:
b00 = User, System, or Supervisor
b01 = Privileged
b10 = User
b11 = any
B 0rwNormal read/write0x0Breakpoint enable:
0 = Breakpoint disabled.
1 = Breakpoint enabled