BLOCKONLY_RST (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BLOCKONLY_RST (CRL_APB) Register Description

Register NameBLOCKONLY_RST
Offset Address0x000000021C
Absolute Address 0x00FF5E021C (CRL_APB)
Width 4
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionRecords the Reason for the Block-only Reset.

BLOCKONLY_RST (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
debug_only 0wtcReadable, write a 1 to clear0x0Only SOC debug will be reset.