BOOT_MODE_POR (CRL_APB) Register Description
| Register Name | BOOT_MODE_POR |
|---|
| Offset Address | 0x0000000204 |
|---|
| Absolute Address |
0x00FF5E0204 (CRL_APB)
|
|---|
| Width | 16 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | Hardware controlled BOOT MODE register. |
|---|
Bit field values are loaded after a POR (internal or PS_POR_B) and cannot change until another POR. The bit fields are triplicated for security. For each field: Captured value of BOOT MODE pins after a POR reset. Since the initial value is defined from the pins, the reset value is listed as 'X.'Register is reset only by a POR reset.
BOOT_MODE_POR (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 15:12 | rwNormal read/write | 0x0 | reserved |
| boot_mode2 | 11:8 | roRead-only | 0 | Set 3 |
| boot_mode1 | 7:4 | roRead-only | 0 | Set 2 |
| boot_mode0 | 3:0 | roRead-only | 0 | Set 1 |