BOOT_MODE_USER (CRL_APB) Register Description
| Register Name | BOOT_MODE_USER |
|---|---|
| Offset Address | 0x0000000200 |
| Absolute Address | 0x00FF5E0200 (CRL_APB) |
| Width | 20 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Software controlled BOOT MODE. |
Register is reset only by a POR reset.
BOOT_MODE_USER (CRL_APB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 19:16 | rwNormal read/write | 0x0 | reserved |
| alt_boot_mode | 15:12 | rwNormal read/write | 0x0 | Alternative Boot Mode value that can be put into the [boot_mode] field. |
| Reserved | 11:9 | rwNormal read/write | 0x0 | reserved |
| use_alt | 8 | rwNormal read/write | 0x0 | Used to control which value is in the [boot_mode] field. 0: POR reset value. 1: Software value [alt_boot_mode] bit field. |
| Reserved | 7:4 | rwNormal read/write | 0x0 | reserved |
| boot_mode | 3:0 | roRead-only | 0 | Boot Mode values from the mode pins captured at POR until software asserts the [use_alt] bit. Once that happens, this bit field will contain the [alt_boot_mode] value written by software. Since the initial value is defined from the Boot Mode pins, the reset value is listed as 'X. |