BRIDGE_CORE_CFG_AXI_MASTER (AXIPCIE_MAIN) Register Description
| Register Name | BRIDGE_CORE_CFG_AXI_MASTER |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address | 0x00FD0E0008 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | AXI Master Max Payload Size Configuration |
BRIDGE_CORE_CFG_AXI_MASTER (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:7 | roRead-only | 0x0 | |
| cfg_m_max_rd_req_size | 6:4 | rwNormal read/write | 0x0 | Maximum read request size allowed for AXI Master Interface read transactions. AXI Master Interface read requests exceeding the configured maximum read request size are fragmented into multiple AXI transactions to comply with the requested max read request size. |
| Reserved | 3 | roRead-only | 0x0 | |
| cfg_m_max_wr_req_size | 2:0 | rwNormal read/write | 0x0 | Maximum write request size allowed for AXI Master Interface write transactions. AXI Master Interface write requests exceeding the configured maximum write request size are fragmented into multiple AXI transactions to comply with the requested max write request size. |