BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT
Offset Address0x000000002C
Absolute Address 0x00FD0E002C (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000BEA
DescriptionAXI Master Write Completion Timeout Configuration

BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0
axi_m_w_tick_count15:0rwNormal read/write0xBEADetermines the AXI Master write request timeout period.
A timeout will occur after 14 to 15 w_ticks with w_ticks occuring at an interval of (256*axi_m_w_tick_count) AXI clocks.
A value of 0 disables the timeout mechanism.
For example axi_m_w_tick_count==7 results in a timeout range of 50.176uS to 53.760uS when the AXI Clock is 500 MHz.