BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT (AXIPCIE_MAIN) Register Description
Register Name | BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT |
---|---|
Offset Address | 0x000000002C |
Absolute Address | 0x00FD0E002C (AXIPCIE_MAIN) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000BEA |
Description | AXI Master Write Completion Timeout Configuration |
BRIDGE_CORE_CFG_AXI_M_W_TICK_COUNT (AXIPCIE_MAIN) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:16 | roRead-only | 0x0 | |
axi_m_w_tick_count | 15:0 | rwNormal read/write | 0xBEA | Determines the AXI Master write request timeout period. A timeout will occur after 14 to 15 w_ticks with w_ticks occuring at an interval of (256*axi_m_w_tick_count) AXI clocks. A value of 0 disables the timeout mechanism. For example axi_m_w_tick_count==7 results in a timeout range of 50.176uS to 53.760uS when the AXI Clock is 500 MHz. |