BRIDGE_CORE_CFG_CRS_RPL_TICK_COUNT (AXIPCIE_MAIN) Register Description
| Register Name | BRIDGE_CORE_CFG_CRS_RPL_TICK_COUNT |
|---|---|
| Offset Address | 0x0000000034 |
| Absolute Address | 0x00FD0E0034 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00002210 |
| Description | PCIe Configuration Write/Read Request CRS Replay Timeout Configuration |
BRIDGE_CORE_CFG_CRS_RPL_TICK_COUNT (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | |
| crs_rpl_tick_count | 15:0 | rwNormal read/write | 0x2210 | Determines the CRS Replay timeout period. AXI Slave Interface initiated PCI Express Configuration Write and Read (ECAM) requests which return Configuration Request Retry Status (CRS), and which are not handled with CRS Software Visbility, will be retried until the timeout period expires. After the timeout expires, the next CRS response received for the transaction is converted to response Slave Error and no longer retried. A timeout will occur after 14 to 15 l_ticks with l_ticks occuring at an interval of (4096*crs_rpl_tick_count) AXI clocks. A value of 0 disables the timeout mechanism. For example crs_rpl_tick_count==8720 results in a timeout range of 1.000S to 1.017S when the AXI Clock is 500 MHz. |