BRIDGE_CORE_CFG_INTERRUPT (AXIPCIE_MAIN) Register Description
| Register Name | BRIDGE_CORE_CFG_INTERRUPT |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00FD0E0010 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PCI Express Core Interrupt Routing Configuration |
BRIDGE_CORE_CFG_INTERRUPT (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | roRead-only | 0x0 | |
| cfg_pcie_int_axi_pcie_n | 0 | rwNormal read/write | 0x0 | Determines whether the interrupt events whose status is recorded in Received Interrupt and Message Controller - Miscellaneous Interrupt Status are routed to PCI Express or AXI. These interrupt sources should generally be routed to the Root Complex unless the local CPU software is designed to handle them. 0: Generate Interrupts to the PCIe Host; 1: Generate Interrupts to the local processor on the AXI side |