BRIDGE_CORE_CFG_PCIE_CREDIT (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_PCIE_CREDIT (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_PCIE_CREDIT
Offset Address0x0000000028
Absolute Address 0x00FD0E0028 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00200200
DescriptionPCI Express Transmit Completion Header and Data Credit Metering Configuration

BRIDGE_CORE_CFG_PCIE_CREDIT (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
cfg_pcie_credit_en31rwNormal read/write0x0Outstanding PCIe read requests are limited to stay within the receive buffer space (CH & CD credits) allocated in the PCI Express Core receive buffer.
cfg_pcie_credit_ch_inf30rwNormal read/write0x0CH Credits Infinite
cfg_pcie_credit_cd_inf29rwNormal read/write0x0CD Credits Infinite
Reserved28:24roRead-only0x0
cfg_pcie_credit_ch_val23:16rwNormal read/write0x20Number of available CH credits.
One CH credit == space for 1 Completion TLP Header.
Reserved15:12roRead-only0x0
cfg_pcie_credit_cd_val11:0rwNormal read/write0x200Number of available CD credits.
One CD credit == space for 16 bytes of Completion TLP Payload.