BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_PCIE_RELAXED_ORDER
Offset Address0x000000001C
Absolute Address 0x00FD0E001C (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000003
DescriptionPCI Express Receive Completion Ordering Configuration

BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2roRead-only0x0
cfg_enable_cfgio_wr_ro 1rwNormal read/write0x1Configuration Write and I/O Write Received Completion Ordering Configuration.
cfg_enable_cfgio_wr_ro == 1 and == 0 are both compliant with PCIe ordering rules as received write transaction passing is permitted but not required for Configuration Writes and I/O Writes.
cfg_enable_dma_ro 0rwNormal read/write0x1PCI Express Received DMA Read Completion Ordering Configuration.
cfg_enable_dma_ro == 1 is not PCIe compliant, however, this optimization is typically fine for most applications and has higher DMA performance due to removing unnecessary transaction blocking.