BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER (AXIPCIE_MAIN) Register Description
Register Name | BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER |
---|---|
Offset Address | 0x000000001C |
Absolute Address | 0x00FD0E001C (AXIPCIE_MAIN) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000003 |
Description | PCI Express Receive Completion Ordering Configuration |
BRIDGE_CORE_CFG_PCIE_RELAXED_ORDER (AXIPCIE_MAIN) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Reserved | 31:2 | roRead-only | 0x0 | |
cfg_enable_cfgio_wr_ro | 1 | rwNormal read/write | 0x1 | Configuration Write and I/O Write Received Completion Ordering Configuration. cfg_enable_cfgio_wr_ro == 1 and == 0 are both compliant with PCIe ordering rules as received write transaction passing is permitted but not required for Configuration Writes and I/O Writes. |
cfg_enable_dma_ro | 0 | rwNormal read/write | 0x1 | PCI Express Received DMA Read Completion Ordering Configuration. cfg_enable_dma_ro == 1 is not PCIe compliant, however, this optimization is typically fine for most applications and has higher DMA performance due to removing unnecessary transaction blocking. |