BRIDGE_CORE_CFG_PCIE_RX0 (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_PCIE_RX0 (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_PCIE_RX0
Offset Address0x0000000000
Absolute Address 0x00FD0E0000 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00010000
DescriptionPCI Express Receive Access and BAR Configuration

BRIDGE_CORE_CFG_PCIE_RX0 (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:18roRead-only0x0
cfg_disable_pcie_dma_reg_access17rwNormal read/write0x0Determines whether DMA Registers are accessible from PCI Express
cfg_disable_pcie_bridge_reg_access16rwNormal read/write0x1Determines whether Bridge Registers are accessible from PCI Express
Reserved15:3roRead-only0x0
cfg_dma_reg_bar 2:0rwNormal read/write0x0Determines which PCI Express Base Address Region (BAR) is used to access DMA and Bridge Registers from PCI Express. If a received PCI Express read/write requests BAR hit information is equal to cfg_dma_reg_bar, then the transaction is terminated by the internal DMA/Bridge Register implementation, otherwise the transaction is forwarded to the AXI Master Interface. cfg_dma_reg_bar is only for received PCI Express read and write requests and has no impact on received AXI Slave Interface requests.