BRIDGE_CORE_CFG_PCIE_RX1 (AXIPCIE_MAIN) Register Description
| Register Name | BRIDGE_CORE_CFG_PCIE_RX1 |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address | 0x00FD0E0004 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PCI Express Receive Transaction Attribute Handling |
BRIDGE_CORE_CFG_PCIE_RX1 (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | roRead-only | 0x0 | |
| cfg_rd_ur_is_ur_ok1s_n | 8 | rwNormal read/write | 0x0 | Determines the AXI response for AXI Slave Interface-initiated PCI Express Configuration read/write transactions that are completed with Unsupported Request status. During Root Port PCI Express hierarchy enumeration, PCI Express software is generally required to issue read and write PCI Express Configuration transactions to PCI Express function numbers that may not exist in order to determine which function numbers have devices present. PCI Express Configuration read/write requests to non-existent functions will return completions with Unsupported Requests status which is considered a serious error for other types of AXI Slave Interface transactions. Since Unsupported Request responses are expected during PCI Express hierarchy enumeration, this register enables such responses to optionally be downgraded in severity. In many cases Root Complex PCI Express Configuration Software will require (cfg_rd_ur_is_ur_ok1s_n == 0) behavior. |
| cfg_pcie_rx_arcache | 7:4 | rwNormal read/write | 0x0 | Value to use for the AXI Master Interface m_arcache port for received PCI Express Memory Read requests, with the No Snoop attribute = 0, that are forwarded to the AXI Master Interface for completion. If a received PCI Express read request that is forwarded to the AXI Master Interface hits an Ingress Translation that has cache attribute replacement enabled, then the Ingress Translation cache value takes priority. |
| cfg_pcie_rx_awcache | 3:0 | rwNormal read/write | 0x0 | Value to use for the AXI Master Interface m_awcache port for received PCI Express Memory Write requests, with the No Snoop attribute = 0, that are forwarded to the AXI Master Interface for completion. If a received PCI Express write request that is forwarded to the AXI Master Interface hits an Ingress Translation that has cache attribute replacement enabled, then the Ingress Translation cache value takes priority. |