BRIDGE_CORE_CFG_PCIE_RX_MSG_FILTER (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_PCIE_RX_MSG_FILTER (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_PCIE_RX_MSG_FILTER
Offset Address0x0000000020
Absolute Address 0x00FD0E0020 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPCI Express Receive Message Filtering Configuration

BRIDGE_CORE_CFG_PCIE_RX_MSG_FILTER (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
cfg_desired_ven_msg_ven_id31:16rwNormal read/write0x0Vendor Defined Message Type 0/1 (Message Code 0x7e & 0x7f) Vendor ID used to perform Vendor ID-specific message filtering.
cfg_desired_ven_msg_ven_inv15rwNormal read/write0x0Selects how to apply Vendor ID-specific filtering.
cfg_desired_ven_msg_en14rwNormal read/write0x0
cfg_enable_oth_msg_fwd13rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] not matching 0x1, 0x2, 0x3, 0x5, or 0x7 (other message types) will be forwarded to the AXI Master Interface. When 0 such messages will be silently dropped and not forwarded.
Reserved12:8roRead-only0x0
cfg_enable_ven_msg_fwd 7rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] not matching 0x1, 0x2, 0x3, 0x5, or 0x7 (other message types) will be forwarded to the AXI Master Interface. When 0 such messages will be silently dropped and not forwarded.
Reserved 6roRead-only0x0
cfg_enable_slt_msg_fwd 5rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] == 0x5 (such as Set Slot Power Limit) will be forwarded to the AXI Master Interface. When 0 such messages will silently be dropped and not forwarded.
Reserved 4roRead-only0x0
cfg_enable_err_msg_fwd 3rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] == 0x3 (such as ERR_COR, ERR_NONFATAL, ERR_FATAL) will be forwarded to the AXI Master Interface. When 0 such messages will be silently dropped and not forwarded.
cfg_enable_int_msg_fwd 2rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] == 0x2 (Assert_INT[A,B,C,D], Deassert_INT[A,B,C,D]) will be forwarded to the AXI Master Interface. When 0 such messages will be silently dropped and not forwarded.
cfg_enable_pm_msg_fwd 1rwNormal read/write0x0When 1, received PCIe messages with msg_code[7:4] == 0x1 (Power Management messages such as PME_Turn_Off, PME_TO_ACK) will be forwarded to the AXI Master Interface. When 0 such messages will be silently dropped and not forwarded.
Reserved 0roRead-only0x0