BRIDGE_CORE_CFG_PCIE_TX (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BRIDGE_CORE_CFG_PCIE_TX (AXIPCIE_MAIN) Register Description

Register NameBRIDGE_CORE_CFG_PCIE_TX
Offset Address0x000000000C
Absolute Address 0x00FD0E000C (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPCI Express Transmit Cut Through Configuration

BRIDGE_CORE_CFG_PCIE_TX (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0
cfg_pcie_tx_cut_through 0rwNormal read/write0x0Enables/Disables cut-through routing for PCIe TLP transmissions. Enabling cut-through routing reduces latency, but may only be enabled when AXI bandwidth is guaranteed to be >= PCI Express bandwidth under all possible conditions.