BRIDGE_CORE_CFG_RQ_REQ_ORDER (AXIPCIE_MAIN) Register Description
| Register Name | BRIDGE_CORE_CFG_RQ_REQ_ORDER |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FD0E0024 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | PCI Express and AXI Read Reorder Queue Completion Ordering Configuration |
BRIDGE_CORE_CFG_RQ_REQ_ORDER (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| cfg_pcie_req_order_strict | 31 | rwNormal read/write | 0x0 | For AXI Master Read Requests. Both 0 & 1 values are compliant with PCIe and AXI ordering requirements. A 1 value will increase read completion latency when read completions are received out of order. The recommended default is 0 and will produce the highest performance. |
| cfg_axi_req_order_strict | 30 | rwNormal read/write | 0x0 | For PCIe Master (Transmitted) Read Requests. Both 0 & 1 values are compliant with PCIe and AXI ordering requirements. A 1 value will increase read completion latency when read completions are received out of order. The recommended default is 0 and will produce the highest performance. |
| Reserved | 29:16 | roRead-only | 0x0 | |
| cfg_axi_req_order_id_mask | 15:0 | rwNormal read/write | 0x0 | Determines which AXI Slave Interface s_arid[SID-1:0] bits are considered when cfg_axi_rq_req_order_strict = 0. * cfg_axi_req_order_id_mask[i] == 1. Consider s_arid[i] when determining the allowed order of read completions to AXI Slave read requests. * cfg_axi_req_order_id_mask[i] == 0. Do not consider s_arid[i] when determining the allowed order of read completions to AXI. |