BTR (CAN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BTR (CAN) Register Description

Register NameBTR
Offset Address0x000000000C
Absolute Address 0x00FF06000C (CAN0)
0x00FF07000C (CAN1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBit Timing and Synchronization

The Bit Timing Register (BTR) specifies the bits needed to configure bit time. Specifically, the Propagation Segment, Phase segment 1, Phase segment 2, and Synchronization Jump Width (as defined in CAN 2.0A, CAN 2.0B and ISO 11891-1) are written to the BTR. The actual value of each of these fields is one more than the value written to this register.

BTR (CAN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9rwNormal read/write0x0Reserved
SJW 8:7rwNormal read/write0x0Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.
TS2 6:4rwNormal read/write0x0Time Segment 2
Indicates Phase Segment 2 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.
TS1 3:0rwNormal read/write0x0Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1 as specified in the CAN 2.0A and CAN 2.0B standard. The actual value is one more than the value written to the register.