BVR1 (R5_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

BVR1 (R5_DBG_0) Register Description

Register NameBVR1
Offset Address0x0000000104
Absolute Address 0x00FEBF0104 (CORESIGHT_R5_DBG_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionBreakpoint Value Register 1

BVR1 (R5_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Breakpoint_value31:0rwNormal read/write0Each BVR is associated with a Breakpoint Control Register(BCR). BCRy is the corresponding control register for BVRy.
A pair of breakpoint registers, BVRy/BCRy, is called a Breakpoint Register Pair
(BRP). BVR0-7 are paired with BCR0-7 to make BRP0-7.
The breakpoint value contained in this register corresponds to either an instruction address or a
context ID. Breakpoints can be set on:
. an instruction address
. a context ID value
. an instruction address and context ID pair.
For an instruction address and context ID pair, two BRPs must be linked. A debug event is generated when both the instruction address and the context ID pair match at the same time.
Note
. Only BRPn supports context ID comparison, where n+1 is the number of breakpoint register pairs implemented in the processor.
. Bits [1:0] of Registers BVR0 to BVR(n-1) are Do Not Modify on writes and Read-As-Zero because these registers do not support context ID comparisons.
. The contents of the CP15 Context ID Register give the context ID value for a BVR to match. For information on the Context ID Register, see Chapter 4 System Control.