CATR1 (DDR_PHY) Register Description
| Register Name | CATR1 |
|---|---|
| Offset Address | 0x0000000244 |
| Absolute Address | 0x00FD080244 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x0103AAAA |
| Description | CA Training Register 1 |
CATR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | roRead-only | 0x0 | Return zeroes on reads. |
| CA0BYTE1 | 27:24 | rwNormal read/write | 0x1 | CA_0 Response Byte Lane 1; Indicates PHY byte lane number to which DRAM byte lane 1 is connected. Valid values are: 4b0000 = CA training responses on DATX8_0 4b0001 = CA training responses on DATX8_1 4b0010 = CA training responses on DATX8_2 4b0011 = CA training responses on DATX8_3 4b0100 = CA training responses on DATX8_4 4b0101 = CA training responses on DATX8_5 4b0110 = CA training responses on DATX8_6 4b0111 = CA training responses on DATX8_7 4b1000 = CA training responses on DATX8_8 |
| CA0BYTE0 | 23:20 | rwNormal read/write | 0x0 | CA_0 Response Byte Lane 0; Indicates PHY byte lane number to which DRAM byte lane 0 is connected. Valid values are: 4b0000 = CA training responses on DATX8_0 4b0001 = CA training responses on DATX8_1 4b0010 = CA training responses on DATX8_2 4b0011 = CA training responses on DATX8_3 4b0100 = CA training responses on DATX8_4 4b0101 = CA training responses on DATX8_5 4b0110 = CA training responses on DATX8_6 4b0111 = CA training responses on DATX8_7 4b1000 = CA training responses on DATX8_8 |
| CAMRZ | 19:16 | rwNormal read/write | 0x3 | Minimum time (in terms of number of dram clocks) for DRAM DQ going tristate after MRW CA exit calibration command. The programmed value must be at least equal to tCAMRZ CA Training parameter in JEDEC spec |
| CACKEH | 15:12 | rwNormal read/write | 0xA | Minimum time (in terms of number of dram clocks) for CKE high after last CA calibration response is driven by memory. The programmed value must be at least equal to tCACKEH CA Training parameter in JEDEC spec |
| CACKEL | 11:8 | rwNormal read/write | 0xA | Minimum time (in terms of number of dram clocks) for CKE going low after CA calibration mode is programmed. The programmed value must be at least equal to tCACKEL CA Training parameter in JEDEC spec |
| CAEXT | 7:4 | rwNormal read/write | 0xA | Minimum time (in terms of number of dram clocks) for CA calibration exit command after CKE is high. The programmed value must be at least equal to tCEXT CA Training parameter in JEDEC spec |
| CAENT | 3:0 | rwNormal read/write | 0xA | Minimum time (in terms of number of dram clocks) for first CA calibration command after CKE is low. The programmed value must be at least equal to tCAENT CA Training parameter in JEDEC spec |