CCER (R5_ETM_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

CCER (R5_ETM_1) Register Description

Register NameCCER
Offset Address0x00000001E8
Absolute Address 0x00FEBFD1E8 (CORESIGHT_R5_ETM_1)
Width32
TyperoRead-only
Reset Value0x0000097A
DescriptionConfiguration Code Extension Register

CCER (R5_ETM_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
All_readable11roRead-only0x1All registers, except some integration test registers, are readable.
Size_of_eextin10:3roRead-only0x2FSize of extended external input bus.
No_of_eextin_sel 2:0roRead-only0x2Number of extended external input selectors.