| Field Name | Bits | Type | Reset Value | Description |
|---|
| P | 31 | rwNormal read/write | 0x0 | EL1 modes filtering bit. Controls counting in EL1. If EL3 is implemented, then counting in Non-secure EL1 is further controlled by the NSK bit. |
| U | 30 | rwNormal read/write | 0x0 | EL0 filtering bit. Controls counting in EL0. If EL3 is implemented, then counting in Non-secure EL0 is further controlled by the NSU bit. |
| NSK | 29 | rwNormal read/write | 0x0 | Non-secure kernel modes filtering bit. Controls counting in Non-secure EL1. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of P, cycles in Non-secure EL1 are counted.Otherwise, cycles in Non-secure EL1 are not counted. |
| NSU | 28 | rwNormal read/write | 0x0 | Non-secure user modes filtering bit. Controls counting in Non-secure EL0. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of U, cycles in Non-secure EL0 are counted.Otherwise, cycles in Non-secure EL0 are not counted. |
| NSH | 27 | rwNormal read/write | 0x0 | Non-secure Hyp modes filtering bit. Controls counting in Non-secure EL2. If EL2 is not implemented, this bit is RES0. |
| M | 26 | rwNormal read/write | 0x0 | Secure EL3 filtering bit. Most applications can ignore this bit and set the value to zero. If EL3 is not implemented, this bit is RES0.If the value of this bit is equal to the value of P, cycles in Secure EL3 are counted.Otherwise, cycles in Secure EL3 are not counted. |