CCNTR_EL0_31to0 (A53_PMU_0) Register Description
Register Name | CCNTR_EL0_31to0 |
---|---|
Offset Address | 0x00000000F8 |
Absolute Address | 0x00FEC300F8 (CORESIGHT_A53_PMU_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Performance Monitors Cycle Counter (low word) |
CCNTR_EL0_31to0 (A53_PMU_0) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
CCNT | 31:0 | rwNormal read/write | 0x0 | Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways:Every processor clock cycle.Every 64th processor clock cycle.The cycle count can be reset to zero by writing 1 to PMCR_EL0.C. |